Method for in-line monitoring of via/contact holes etch...

Details Method for in-line monitoring of via/contact holes etch... Method for in-line monitoring of via/contact holes etch...

Filed on

2006-09-12

Date issued

2006-09-12

Examiner

Dang, Phuc T. (Department: 2818)

Patent Class

Semiconductor device manufacturing: process

SubClass

Coating with electrically or thermally conductive material

SubSubClass

To form ohmic contact to semiconductive material

Other Related Categories

C438S735000

Type

Reexamination Certificate

Status

active

Patent number

07105436

Description

ABSTRACT:
A method for in-line monitoring of via/contact etching process based on a test structure is described. The test structure is comprised of via/contact holes of different sizes and densities in a layout such that, for a certain process, the microloading or RIE lag induced non-uniform etch rate produce under-etch in some regions and over-etch in others. A scanning electron microscope is used to distinguish these etching differences in voltage contrast images. Image processing and simple calibration convert these voltage contrast images into a “fingerprint” image characterizing the etching process in terms of thickness over-etched or under-etched. Tolerance of shifting or deformation of this image can be set for validating the process uniformity. This image can also be used as a measure to monitor long-term process parameter shifting, as well as wafer-to-wafer or lot-to-lot variations. Advanced process control (APC) can be performed in-line with the guidance of this image so that potential electrical defects are avoided and process yield ramp accelerated.

REFERENCES:
patent: 2003/0096436 (2003-05-01), Satya et al.

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