Semiconductor memory device and manufacturing method thereof

Details Semiconductor memory device and manufacturing method thereof Semiconductor memory device and manufacturing method thereof

2006-04-11

2006-04-11

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000

Reexamination Certificate

active

07026674

ABSTRACT:
A semiconductor memory device includes a capacitor which comprises a ferroelectric layer with the perovskite crystal structure which, being expressed by the general formula ABO3, contains lead (Pb) as the element A occupying lattice A and zirconium (Zr) and titanium (Ti) as the element B occupying lattice B, and a lower electrode and an upper electrode which are disposed to sandwich the ferroelectric layer. The ferroelectric layer has, both on the side of the lower electrode and on the side of the upper electrode, a region each, in which a ratio of Zr to Ti (a Zr/Ti ratio) is equal to or greater than a Zr/Ti ratio of the central section of the ferroelectric layer in the direction of thickness, and the Zr/Ti ratio of at least one of the regions on the side of the lower electrode and on the side of the upper electrode is greater than the Zr/Ti ratio of the central section.

REFERENCES:
patent: 6165622 (2000-12-01), Kijima et al.
patent: 6841817 (2005-01-01), Kurasawa et al.
patent: 2000-31399 (2000-01-01), None
patent: 2000-58525 (2000-02-01), None
patent: 2000-67650 (2000-03-01), None
patent: 2003-142659 (2003-05-01), None

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