Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2006-08-08
2006-08-08
Nguyen, VanThu (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S230080
Reexamination Certificate
active
07088633
ABSTRACT:
A memory system is provided. The system includes a volatile memory having a number of banks and configured to engage in one of a number of operating modes including an auto-refresh mode and a self-refresh mode, and a memory controller configured to direct the volatile memory to engage in one of the operating modes. Upon the memory controller directing the volatile memory to engage in the self-refresh mode, the memory controller is further configured to provide an entry bank address to the volatile memory, the entry bank address corresponding to the first bank that is to be refreshed during the self-refresh mode. Upon the volatile memory exiting the self-refresh mode, the volatile memory is further configured to make an exit bank address available to the memory controller, the exit bank address corresponding to the last bank that was refreshed prior to the volatile memory exiting the self-refresh mode.
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patent: 6310814 (2001-10-01), Hampel et al.
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Remaklus, Jr. Perry Willmann
Walker Robert Michael
Brown Charles D.
Nguyen Van-Thu
Pauley Nicholas J.
QUALCOMM Incorporated
Wadsworth Philip R.
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