Topological vias route wherein the topological via does not...

Details Topological vias route wherein the topological via does not... Topological vias route wherein the topological via does not...

2006-08-08

2006-08-08

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07089524

ABSTRACT:
Some embodiments of the invention provide a method for generating multi-layer topological routes in a region of a design layout. The method selects a net that has routable elements on a several interconnect layers. For the selected net, the method defines a topological route that connects the selected net's routable elements. The topological route includes a topological via that specifies the defined route's traversal from one interconnect layer to another interconnect layer, without having a coordinate within the region.

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