Floating-body DRAM with two-phase write

Details Floating-body DRAM with two-phase write Floating-body DRAM with two-phase write

2006-07-04

2006-07-04

Mai, Son (Department: 2827)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S149000, C365S174000, C365S182000, C365S184000, C365S186000

Reexamination Certificate

active

07072205

ABSTRACT:
A row of floating-body single transistor memory cells is written to in two phases.

REFERENCES:
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patent: 6873539 (2005-03-01), Fazan et al.
patent: 2004/0021137 (2004-02-01), Fazan et al.
Fazan, Pierre, et al., “A Simple 1-Transistor Capacitor-Less Memory Cell for High Performance Embedded DRAMs”,IEEE 2002 Custom Integrated Circuits Conference, (2002),99-102.
Ohsawa, Takashi, et al., “A Memory Using One-Transistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAMs”,2003 Symposium on VLSI Circuits Digest of Technical Papers, (2003),4 pages.
Ohsawa, Takashi, et al., “Memory Design Using a One-Transistor Gain Cell on SOI”,IEEE Journal of Solid-State Circuits, vol. 37, No. 11, (Nov. 2002),1510-1522.
Ohsawa, Takashi, et al., “Memory Design Using One-Transistor Gain Cell on SOI”,ISSCC 2002, Session 9, Dram and Ferroelectric Memories, 9.1, (Feb. 5, 2002),3 pages.
Okhonin, S., “A Capacitor-Less 1T-DRAM Cell”,IEEE Electron Device Letters, vol. 23, No. 2, (Feb. 2002),85-87.
Okhonin, S., et al., “A SOI Capacitor-less 1T-DRAM Concept”,2001 IEEE International SOI Conference, (Oct. 2001),153-154.

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