Device for the emulation of designs for integrated circuits

Details Device for the emulation of designs for integrated circuits Device for the emulation of designs for integrated circuits

2006-08-29

2006-08-29

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C326S041000

Reexamination Certificate

active

07100130

ABSTRACT:
A device for the emulation of designs for integrated circuits having a receiving device for multiple programmable logic circuits, particularly FPGAs, and an electrical connection structure. The interconnection structure has bus lines, each of which includes multiple channels. The interconnection structure is configured so that each programmable logic circuit is connected to at least one bus line and the connection structure is implemented so it can be flexibly interconnected, wherein the assignment of at least a part of the terminal contacts of any programmable logic circuit is freely programmable and wherein at least a part of the bus lines connected to the programmable logic circuits are alternately electrically connectable to one another in such a way that at least one channel of a bus line is electrically connectable to a channel of at least one other bus line using a switch.

REFERENCES:
patent: 5742181 (1998-04-01), Rush
patent: 6263484 (2001-07-01), Yang
Hauck, IEEE Proceedings “The Roles of FPGA's in Reprogrammable Systems”, Apr. 1, 1998, vol. 86, No. 4.
Carrera, J M et al., “Architecture of a FPGA-based Coprocessor”: the PAR-1 1995 IEEE.
Khalid, Mohammed A. S., “Routing Architecture and Layout Synthesis For Multi-FPGA Systems”, 1999, University of Toronto, Canada.

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