Method and apparatus for implementing thread replacement for...

Electrical computers and digital processing systems: virtual mac – Task management or control – Process scheduling

Reexamination Certificate

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C712S001000, C712S216000, C712S228000, C712S233000

Reexamination Certificate

active

07096470

ABSTRACT:
A method and apparatus are provided for implementing thread replacement for optimal performance in a two-tiered multithreading structure. A first tier thread state storage stores a limited number of runnable thread register states. A second tier thread storage facility stores a second number of thread states that is greater than the limited number of runnable thread register states. Each stored thread state includes predefined selection data. A runnable thread selection logic coupled between the first tier thread state storage and the second tier thread storage facility, uses the stored predefined selection data for selectively exchanging thread states between the first tier limited number of runnable thread register states and the second tier thread storage facility.

REFERENCES:
patent: 5692192 (1997-11-01), Sudo
patent: 5771382 (1998-06-01), Wang et al.
patent: 5812811 (1998-09-01), Dubey et al.
patent: 5815727 (1998-09-01), Motomura
patent: 5872963 (1999-02-01), Bitar et al.
patent: 6018759 (2000-01-01), Doing et al.
patent: 6076157 (2000-06-01), Borkenhagen et al.
patent: 6105051 (2000-08-01), Borkenhagen et al.
patent: 6212544 (2001-04-01), Borkenhagen et al.
patent: 6223208 (2001-04-01), Kiefer et al.
patent: 6418460 (2002-07-01), Bitar et al.
patent: 6567839 (2003-05-01), Borkenhagen et al.
patent: 6662204 (2003-12-01), Watakabe et al.
patent: 6697935 (2004-02-01), Borkenhagen et al.
patent: 6766515 (2004-07-01), Bitar et al.
patent: 6785889 (2004-08-01), Williams
patent: 6965986 (2005-11-01), Kossman et al.
patent: 61-187116 (1986-08-01), None
patent: 08-164867 (1996-06-01), None
patent: 09-006007 (1997-01-01), None
patent: 09-194346 (1997-07-01), None
patent: 10-320759 (1998-11-01), None
patent: 2000-333724 (2000-10-01), None
Shen et al., “Adaptive Two-Level Thread Management for Fast MPI Execution on Shared Memory Machines”, ACM, 1999, pp. 1-19.
Kraiss et al., “Intergrated Document Caching and Prefetching in Storage Hierarchies Based on Markov-Chain Predictions”, The VLDB Journal, 1998, pp. 141-162.
U.S. Appl. No. 10/246,937, filed Sep. 19, 2002.
“Method and Apparatus for Implementing Two-Tiered Thread State Multithreading Support with High Clock Rate”.

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