Semiconductor device, and wiring-layout design system for...

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means

Reexamination Certificate

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Details

C257S203000, C257S737000, C257S758000

Reexamination Certificate

active

07049642

ABSTRACT:
In a semiconductor device having a plurality of area sections defined therein, a basic multi-layered wiring arrangement is provided on a semiconductor substrate, and both the substrate and the basic multi-layered wiring arrangement have an internal electronic circuit area section and an I/O area section defined in each of the area sections. A plurality of electronic circuits are produced in the circuit area section, and an I/O buffer is produced in the I/O area section. The I/O buffer is suitably and electrically connected to the internal electronic circuits in the basic arrangement. An external multi-layered wiring arrangement is provided on the basic arrangement, and has a power supply electrode pad, a ground electrode pad, at least one signal electrode pad formed and arranged on a top surface thereof, and a wiring-layout produced therein to establish electrical connections between the I/O buffer and the electrode pads. The wiring-layout includes a plurality of conductive paths for establishing the electrical connection between the I/O buffer and the power supply electrode pad, a plurality of conductive paths for establishing the electrical connection between the I/O buffer and the ground electrode pad, and a conductive path for establishing the electrical connection between the I/O buffer and the signal electrode pad, and all the conductive paths feature the same width as each other.

REFERENCES:
patent: 6-061428 (1994-03-01), None
patent: 2001-060625 (2001-03-01), None

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