Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-05-23
2006-05-23
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
07051297
ABSTRACT:
The present invention is directed to a method and apparatus for mapping platform-based design to multiple foundry processes. According to an exemplary aspect of the present invention, a predefined (or pre-specified) slice is successfully mapped on to a first fabrication process with a first set of design rules to produce a first result. Then the slice's ability to be mapped to a second fabrication process with a second set of design rules is evaluated to produce a second result. Next, the comparison between the two results is computed to produce a third result. The third result may be then used to modify the slice architecture, optimize the metalization process and/or modify the first or second fabrication process. The slice definition, the first set of design rules, the second set of design rules, the first result, the second result, and the third result may be stored into a database. With such a database established, new platform-based designs may be mapped to existing foundries, and existing platform-based designs may be mapped to new foundries within a time interval (e.g., hours) much shorter than the 18 months required by typical manual mapping processes.
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Levin Naum B.
LSI Logic Corporation
Suiter - West PC LLO
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