Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2006-07-04
2006-07-04
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S170000, C365S230010, C365S230060, C365S230080
Reexamination Certificate
active
07073039
ABSTRACT:
A degree of local addressing is provided for a processing element array by partitioning a register file memory (e.g., data columns, data rows), and adding a select column or row to be associated with each block. The select column or row allows each processing element to read data from or to write data to a different register file address. Global addressing may also be implemented by reading data from or writing data to the same register file address for each processing element. The invention provides the advantage of faster overall execution time. In addition, there is minimal additional area overhead because of the need to pitch match the processing element array to a main memory.
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Fish & Neave IP Group Ropes & Gray LLP
Micro)n Technology, Inc.
Peugh Brian R.
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