Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2006-09-05
2006-09-05
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S702000, C438S132000, C438S601000
Reexamination Certificate
active
07101804
ABSTRACT:
A method for forming a fuse includes forming an interconnection pattern and a fuse pattern on a substrate using a damascene process. A passivation layer is formed on a surface of the substrate over the interconnection pattern and the fuse pattern. Then, the passivation layer is patterned to form a pad opening that exposes a portion of the interconnection pattern. A metal pad is formed on the interconnection pattern in the pad opening. A portion of the metal pad extends over the passivation layer. The passivation layer on the fuse pattern is partially etched to form a fuse opening.
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Choi Ja-Young
Lee Ki-Young
Chen Kin-Chan
Marger & Johnson & McCollom, P.C.
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