Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-07-18
2006-07-18
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07080337
ABSTRACT:
An embodiment of the present invention includes a method of providing a non-uniform distribution of decoupling capacitors to provide a more uniform noise level across the chip. Leads on a packaged semiconductor chip are grouped into two or more regions. Types of leads needing decoupling capacitors are grouped into lead categories. For each region, there may be one or more lead categories therein. One or more decoupling capacitors are preferably assigned to each lead category in each region. Calculations may be performed to estimate a desired capacitance for each decoupling capacitor for each lead category in each region. When a chip has different components operating at different switching frequencies, different voltages, and/or different switching currents, the distribution of the decoupling capacitors will likely be non-uniform to provide a more uniform noise level across the chip, as compared to a uniform distribution of decoupling capacitors for the chip.
REFERENCES:
patent: 6385565 (2002-05-01), Anderson et al.
Jung, S., et al., “Packaging Consideration for 1 Gbps Si CMOS Optical Driver,” IEEE (2000) pp. 882-883.
Fan, J., et al., “Quantifying Decoupling Capacitor Location,” IEEE (Feb. 2000) pp. 761-766.
Brady III Wade James
Do Thuan
Tung Yingsheng
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