Gate controlled floating well vertical MOSFET

Details Gate controlled floating well vertical MOSFET Gate controlled floating well vertical MOSFET

2006-09-05

2006-09-05

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S185240, C257S220000

Reexamination Certificate

active

07102914

ABSTRACT:
A novel transistor structure for a DRAM cell includes two deep trenches, one trench including a vertical storage cell for storing the data and the second trench including a vertical control cell for controlling the p-well voltage, which, in effect, places part of the p-well in a floating condition thus decreasing the threshold voltage as compared to when the vertical pass transistor is in an off-state. This enables the transistor to exhibit increased gate overdrive and drive current during an active wordline voltage commonly applied to both gates of the storage and control cells.

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