Method of fabricating a vertical quadruple conduction...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S331000, C257S401000

Reexamination Certificate

active

07078764

ABSTRACT:
The vertical insulated gate transistor includes, on a semiconductor substrate, a vertical pillar incorporating one of the source and drain regions at the top, a gate dielectric layer situated on the flanks of the pillar and on the top surface of the substrate, and a semiconductor gate resting on the gate dielectric layer. The other of the source and drain regions is in the bottom part of the pillar PIL and the insulated gate includes an isolated external portion15resting on the flanks of the pillar and an isolated internal portion14situated inside the pillar between the source and drain regions. The isolated internal portion is separated laterally from the isolated external portion by two connecting semiconductor regions PL1,PL2extending between the source and drain regions, and forming two very fine pillars.

REFERENCES:
patent: 5480838 (1996-01-01), Mitsui
patent: 5656842 (1997-08-01), Iwamatsu et al.
patent: 5708286 (1998-01-01), Uesugi et al.
patent: 5965914 (1999-10-01), Miyamoto
patent: 6020239 (2000-02-01), Gambino et al.
patent: 6312992 (2001-11-01), Cho
patent: 6440801 (2002-08-01), Furukawa et al.
patent: 6528405 (2003-03-01), Martinez et al.
patent: 6587396 (2003-07-01), Jang
patent: 04264776 (1992-09-01), None
patent: 04294585 (1992-10-01), None
French Preliminary Search Report dated Feb. 6, 2002 for French Application No. 0104437.

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