Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2006-04-18
2006-04-18
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S730000, C714S738000
Reexamination Certificate
active
07032141
ABSTRACT:
A test interface circuit, which has a simple pattern generator mounted on a semiconductor device having a mounted memory, consists of a command analysis section which analyses a command of three bits received from a tester, outputs an analysis result to a memory core and controls an operation of the memory core, and an address counter which counts addresses and outputs the addresses to the memory core in accordance with a counter control instruction of two bits received from the tester. It is, therefore, possible to make a circuit for testing the memory core small in scale and to decrease the number of pins for testing the memory core, so that it is possible to use an inexpensive tester and to reduce cost required to test the memory core.
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Masaru Haraguchi, et al, “A Semiconductor Test Circuit for Testing a Semiconductor Memory Device Having a Write Mask Function” U.S. Appl. No. 10/122,365, Filed Apr. 16, 2002.
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Alphonse Fritz
De'cady Albert
McDermott Will & Emery LLP
Renesas Technology Corp.
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