Data processing device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data pulse evaluation/bit decision

Reexamination Certificate

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Details

C714S814000

Reexamination Certificate

active

06990615

ABSTRACT:
A data and clock recovery circuit is provided for generating a recovered version of a transmitted data stream. The data and clock recovery circuit comprises three main circuit modules, namely a data recovery circuit, a clock recovery circuit, and a detector circuit. The data recovery circuit is arranged to receive a data stream, and to generate therefrom an estimate of the signal levels for each bit-period of the originally transmitted data stream. The estimates of the signal levels are stored within the data recovery circuit and are sampled by the clock recovery circuit so that the original data stream is recovered. The data recovery circuit is also arranged to generate a so-called “word metric” which is a quality factor representing the accuracy of the estimated signal levels. The clock recovery circuit is arranged to use both the received data stream, and the word metric generated in the data recovery circuit, to determine whether or not the current sampling time is optimal. If not, the current sampling time is adjusted so that it moves towards an “ideal” sampling time. The detector circuit, which may correspond to a correlator in some embodiments, is arranged to determine when the start of a new data stream is received.

REFERENCES:
patent: 6137844 (2000-10-01), Maresca
patent: 6263035 (2001-07-01), Maresca
patent: 6272183 (2001-08-01), Berens et al.
patent: 6738364 (2004-05-01), Saunders
patent: 2003/0061564 (2003-03-01), Maddux
patent: 0 317 159 (1989-05-01), None
patent: 0 551 596 (1993-07-01), None
patent: 0 551 695 (1993-07-01), None
UK Search Report, GB 0204209.1, Pending.

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