Process for designing comparators and adders of small depth

Details Process for designing comparators and adders of small depth Process for designing comparators and adders of small depth

2006-03-28

2006-03-28

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07020865

ABSTRACT:
Logic circuits for logical operations, based on a function fN=x1OR (x2AND (x3OR (x4AND . . . xN. . . ))) or f′N=x1AND (x2OR (x3AND (x4OR . . . xN. . . ))), are designed by defining a top portion of the logic circuit based on a pre-selected pattern of 2-input $ and @ gates. The top portion has N inputs and approximately N/3 outputs. A smaller logic circuit is defined having approximately N/3 inputs coupled to the outputs of the top portion. In one embodiment, the circuit is designed for a circuit having N′ inputs, where N′ is 3nor 2*3n, and the N′−N most significant inputs are set to fixed values. The extra gates are removed resulting in a minimum depth circuit. In another embodiment, the depth is further reduced in some cases by designing a circuit for N−1 inputs and transforming the circuit to an N-input circuit. The $ and @ gates are converted to AND and/or OR gates, depending on the function.

REFERENCES:
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Cortadella, “Timing-Driven Logic Bi-Decomposition”, Jun. 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits, vol. 22, iss. 6, pp. 675-685.
U.S. Appl. No. 10/017,802, Optimization of Comparator Architecture, filed Dec. 12, 2001.
U.S. Appl. No. 10/017,792, Opitimziation of an Adder Based Circuit Architecture, filed Dec. 12, 2001.

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