Electrical computers and digital data processing systems: input/ – Interrupt processing
Reexamination Certificate
2006-01-17
2006-01-17
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Interrupt processing
C710S104000, C710S125000, C710S118000, C710S262000
Reexamination Certificate
active
06988156
ABSTRACT:
A system and method for dynamically tuning the interrupt coalescing behavior of a communication interface. An interrupt handler adjusts dynamic Packet and/or Latency values to control how many packets the interface may accumulate, or how much time the interface may wait after receiving a first packet, before it can signal a corresponding interrupt to a host processor and forward the accumulated packet(s). The interrupt handler maintains a Trend parameter reflecting a comparison between recent sets of packets received from the interface and the Packet parameter. The Packet value is decreased or increased as packet traffic ebbs or flows. When the Packet value is incremented from a minimum value, a Fallback mechanism may be activated to ensure a relatively rapid return to the minimum value if an insufficient amount of traffic is received to warrant a non-minimum Packet value. The Latency value may be increased as the processor's workload increases.
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Auve Glenn A.
Mason Donna K.
Park Vaughan & Fleming LLP
Sun Microsystems Inc.
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