Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-04-04
2006-04-04
Bataille, Pierre Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S123000, C711S129000, C711S119000
Reexamination Certificate
active
07024519
ABSTRACT:
Methods and apparatus for controlling hierarchical cache memories permit: controlling a first level cache memory including a plurality of cache lines, each cache line being operable to store an address tag and data; controlling a next lower level cache memory including a plurality of cache lines, each cache line being operable to store an address tag, status flags, and data, the status flags of each cache line including an L-flag; and setting the L-flag of a given cache line of the next lower level cache memory to indicate whether or not a corresponding one the of the cache lines of the first level cache memory has been refilled with a copy of the data stored in the given cache line of the next lower level cache memory.
REFERENCES:
patent: 3576544 (1971-04-01), Cordero, Jr. et al.
patent: 4037214 (1977-07-01), Birney et al.
patent: 4332009 (1982-05-01), Gerson
patent: 4422088 (1983-12-01), Gfeller
patent: 4430705 (1984-02-01), Cannavino et al.
patent: 4545016 (1985-10-01), Berger
patent: 4589064 (1986-05-01), Chiba et al.
patent: 4732446 (1988-03-01), Gipson et al.
patent: 4903234 (1990-02-01), Sakuraba et al.
patent: 4939682 (1990-07-01), Falk
patent: 4954982 (1990-09-01), Tateishi et al.
patent: 5144691 (1992-09-01), August et al.
patent: 5159700 (1992-10-01), Reid et al.
patent: 5216633 (1993-06-01), Weon et al.
patent: 5261066 (1993-11-01), Jouppi et al.
patent: 5268973 (1993-12-01), Jenevein
patent: 5513337 (1996-04-01), Gillespie et al.
patent: 5619671 (1997-04-01), Bryant et al.
patent: 5649154 (1997-07-01), Kumar et al.
patent: 5671391 (1997-09-01), Knotts
patent: 5715428 (1998-02-01), Wang et al.
patent: 5729712 (1998-03-01), Whittaker
patent: 5848435 (1998-12-01), Brant et al.
patent: 5850534 (1998-12-01), Kranich
patent: 5900019 (1999-05-01), Greenstein et al.
patent: 5991858 (1999-11-01), Weinlander
patent: 6035381 (2000-03-01), Mita et al.
patent: 6076149 (2000-06-01), Usami et al.
patent: 6467012 (2000-10-01), Alvarez et al.
patent: 6212605 (2001-04-01), Arimilli et al.
patent: 6247094 (2001-06-01), Kumar et al.
patent: 6351789 (2002-02-01), Green
patent: 6356980 (2002-03-01), Arimilli et al.
patent: 2002/0087815 (2002-07-01), Arimilli et al.
patent: 0 461 926 (1991-12-01), None
patent: 0840231 (1998-05-01), None
patent: 0817080 (1998-07-01), None
patent: 54-146555 (1979-11-01), None
patent: 56-123051 (1981-09-01), None
patent: 63-019058 (1988-01-01), None
patent: 11-039215 (1999-02-01), None
Jim Handy, “The cache Memory Book: the authoritative reference on cache design,” 2nd edition, Academic Press, 1993.
IBM Wins Playstation 3 Contract, BBC News, Mar. 12, 2001.
U.S. Appl. No. 09/815,554, filed Mar. 22, 2001, entitled System and Method for Data Synchronization for a Computer Architecture for Broadband Networks, to Suzuoki et al.
Baer J-L et al., “On The Inclusion Properties For Multi-Level Cache Hierarchies,” Proceedings of the Annual International Symposium on Computer Architecture, Honolulu, May 30-Jun. 2, 1998, Washington, IEEE Comp. Soc. Press., vol. Symp. 15, pp. 73-80.
Bataille Pierre Michel
Lerner David Littenberg Krumholz & Mentlik LLP
Sony Computer Entertainment Inc.
Tsai Sheng-Jen
LandOfFree
Methods and apparatus for controlling hierarchical cache memory does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods and apparatus for controlling hierarchical cache memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for controlling hierarchical cache memory will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3571444