Memory device and method of manufacturing a memory device

Details Memory device and method of manufacturing a memory device Memory device and method of manufacturing a memory device

2006-04-25

2006-04-25

Wilson, Christian D. (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Plural dram cells share common contact or common trench

C257S903000, C257S906000, C257S908000, C365S149000

Reexamination Certificate

active

07034408

ABSTRACT:
A memory device includes a DRAM memory cell array, which is implemented as a 6 F×F array, and peripheral circuitry. The word lines of the memory cell array are implemented as buried word lines, and, in addition, the bit lines including the bit line contacts are made of a bit line layer stack. The peripheral circuitry includes a peripheral transistor including first and second source/drain regions, a channel connecting the first and the second source/drain regions as well as a peripheral gate electrode for controlling an electrical current of the channel. The peripheral gate electrode is made of a peripheral gate stack including a layer stack which is identical with the bit line stack.

REFERENCES:
patent: 5502320 (1996-03-01), Yamada
patent: 6191975 (2001-02-01), Shimizu et al.
patent: 6419948 (2002-07-01), Blume et al.
patent: 6545904 (2003-04-01), Tran
patent: 6635918 (2003-10-01), Narui et al.
patent: 6785157 (2004-08-01), Arimoto et al.
patent: WO 01/01489 (2000-04-01), None

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