Semiconductor device and manufacturing method of the same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S204000, C257S250000

Reexamination Certificate

active

07112858

ABSTRACT:
An aspect of the present invention provides a semiconductor device that includes a first transistor including a source region, a drain region provided in the same device region as the source region, and a loop-shaped gate electrode region, and a second transistor sharing, with the first transistor, the loop-shaped gate electrode region and the source region or the drain region.

REFERENCES:
patent: 6057568 (2000-05-01), Kumagai
patent: 6140687 (2000-10-01), Shimomura et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6888207 (2005-05-01), Hebert
patent: 7-202146 (1995-08-01), None
Yang-Kyu Choi, et al., “Sub-20nm CMOS FinFET Technologies”, International Electron Devices Meeting (IEDM) Tech. Dig., Dec. 2001, pp. 421-424.
Bin Yu, et al., “FinFET Scaling to 10nm Gate Length”, International Electron Devices Meeting (IEDM) Tech. Dig., Dec. 2002, pp. 251-254.

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