Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Including signal comparison

Reexamination Certificate

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C365S207000

Reexamination Certificate

active

07027334

ABSTRACT:
A semiconductor memory device includes: a device substrate having a semiconductor layer separated by a dielectric layer from a base substrate; a memory cell array having a plurality of memory cells formed and arranged on the semiconductor layer of the device substrate, each the memory cell having a MOS transistor structure with a body in an electrically floating state to store data based on a majority carrier accumulation state of the body; and a sense amplifier circuit configured to read out data of a selected memory cell in the memory cell array to store the read data in a data latch, then transfer the read data to an output circuit and write back the read data into the selected memory cell.

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T. Ohsawa, et al., ISSCC 2002 / Session 9 / Dram and Ferroelectric Memories 9. 1, pp. 152-153, “Memory Design Using One-Transistor Gain Cell on SOI”, 2002.
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U.S. Appl. No. 10/854,403, filed May 14, 2004, Yamada et al.
Pierre C. Fazan et al., “A Simple 1-Transistor Capacitor-Less Memory Cell for High Performance Embedded DRAMs”, IEEE 2002 Custom Integrated Circuits Conference, pp. 7-1-1 to 7-1-4.

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