Memory cell structures including a gap filling layer and...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C438S257000

Reexamination Certificate

active

07105887

ABSTRACT:
Memory cell structures and methods of fabricating the same are disclosed. An illustrated fabrication method comprises: forming spacers to isolate and protect a gate area (including a floating gate and a control gate); forming a gap filling layer over a substrate including the gate area and the spacers; and depositing an insulating layer over the gate area and the gap filling layer. The spacers may be formed of SiN. The gap filling layer may be formed by depositing undoped polysilicon or amorphous silicon over the gate area and the spacers, and by performing an anisotropic etching of the undoped polysilicon or amorphous silicon.

REFERENCES:
patent: 5514900 (1996-05-01), Iranmanesh
patent: 5970335 (1999-10-01), Helm et al.
patent: 6475895 (2002-11-01), Mei et al.
patent: 6624024 (2003-09-01), Prall et al.

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