ESD protection device for high voltage

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Lateral bipolar transistor structure

Reexamination Certificate

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C257SE29173

Reexamination Certificate

active

07081662

ABSTRACT:
An electrostatic discharge (ESD) protection structure and a method for forming the same are provided. The structure includes a substrate having a buried layer, and a first and a second high-voltage well region on the buried layer. The first and second high-voltage well regions have opposite conductivity types and physically contact each other. The structure further includes a field region extending from the first high-voltage well region into the second high-voltage well region, a first doped region in the first high-voltage well region and physically contacting the field region, and a second doped region in the second high-voltage well region and physically contacting the field region. The first and second doped regions and the first high-voltage well region form a bipolar transistor that can protect an integrated circuit from ESD.

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Lin, K.-H., et al., “Design on Latchup-Free Power-Rail ESD Clamp Circuit in HIgh-Voltage CMOS ICs,” EOS/ESD Symposium, 2004, pp. 265-271.

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