Method and arrangement for testing output circuits of high...

Details Method and arrangement for testing output circuits of high... Method and arrangement for testing output circuits of high...

2006-03-21

2006-03-21

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S233100

Reexamination Certificate

active

07016244

ABSTRACT:
For testing or for characterizing output drivers of output circuits of high-speed semiconductor memory devices under conditions close to an application, scan elements are provided at the inputs of the output circuits. The scan elements in each case have a register function and are cascaded to form a scan chain. Via the scan chain, test data signals are applied to the inputs of the output circuits whilst bypassing a memory cell array of the semiconductor memory devices. The characterization of data signals of the high-speed semiconductor memory devices that are output by the output circuits requires only a test memory controller not connected to the data signal terminals and a passive load simulation of the application memory controller.

REFERENCES:
patent: 5592493 (1997-01-01), Crouch et al.
patent: 5821786 (1998-10-01), Nozuyama et al.
patent: 6560147 (2003-05-01), Yoshiyama
patent: 2003/0058165 (2003-03-01), Whetsel, Jr.

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