Semiconductor memory device and method for writing data into...

Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition

Reexamination Certificate

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C365S185010

Reexamination Certificate

active

07107389

ABSTRACT:
A source block (B0) and the logical page number (“8”) of a write target page are identified from the logical address of the write target page. Data objects (DN8,DN9, . . . , DN12) to be written, which a host stores in a page buffer (2), are written into the data areas (DA) of the pages (Q0,Q1, . . . , Q4) of a destination block (Bn), starting from the top page (Q0) in sequence. The logical page number (“8”) of the write target page is written into the redundant area (RA) of the top page (Q0). The physical page number (“6=8−2”) of the write target page is identified, based on the logical page number (“8”) of the write target page and the page offset (“2”) of the source block (B0). When notified by the host of the end of the sending of the data objects (DN8, . . . , DN12), the data items (D13, . . . , D31,D0,D1, . . . , D7) in the source block (B0) are transferred to the pages (Q5,Q6, . . . , Q31) in the destination block (Bn) via the page buffer (2) sequentially and cyclically, starting from the page (P11) situated cyclically behind the write target page (P6) by the number (“5”) of pages of the data objects (DN8, . . . , DN12).

REFERENCES:
patent: 5611067 (1997-03-01), Okamoto et al.
patent: 6141726 (2000-10-01), Dell
patent: 6763424 (2004-07-01), Conley
patent: 6938116 (2005-08-01), Kim et al.
patent: 09282111 (1997-10-01), None

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