Methods and apparatus for active termination of...

Details Methods and apparatus for active termination of... Methods and apparatus for active termination of...

2006-03-28

2006-03-28

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S033000

Reexamination Certificate

active

07019554

ABSTRACT:
An integrated circuit includes at least one main circuit313operable to perform one or more functions. At least one termination node DQ receives or transmits an operating signal. An active termination circuit301has first and second transistors of opposite type coupled in series between a Vdd node of a first source potential and a Vss node of a second source potential. The at least one termination node is coupled to a common node between the first and second transistors. A control circuit operates to bias the first and second transistors such that they exhibit a controlled impedance at the common node. Alternatively, the control circuit operates to bias the first and second transistors such that they provide a clamping function at the common node.

REFERENCES:
patent: 5955911 (1999-09-01), Drost et al.
patent: 6072331 (2000-06-01), Takizawa
patent: 6388495 (2002-05-01), Roy et al.
patent: 6836144 (2004-12-01), Bui et al.
P.R. Gray, et al., “Analysis and Design of Analog Integrated Circuits” ISBN 0-471-87493-0, 1984 Second Edition, pp. 59-67, John Wiley & Sons, Inc., New York, no month.

Affiliated with

Also associated with

Rating

Methods and apparatus for active termination of... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Methods and apparatus for active termination of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods and apparatus for active termination of... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3556767