Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
2006-07-11
2006-07-11
Tsai, Henry W. H. (Department: 2181)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S233000
Reexamination Certificate
active
07076640
ABSTRACT:
A processor avoids or eliminates repetitive replay conditions and frequent instruction resteering through various techniques including resteering the fetch after the branch instruction retires, and delaying branch resolution. A processor resolves conditional branches and avoids repetitive resteering by delaying branch resolution. The processor has an instruction pipeline with inserted delay in branch condition and replay control pathways. For example, an instruction sequence that includes a load instruction followed by a subtract instruction then a conditional branch, delays branch resolution to allow time for analysis to determine whether the condition branch has resolved correctly. Eliminating incorrect branch resolutions prevents flushing of correctly predicted branches.
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U.S. Appl. No. 60/355,464.
Copy of International Search Report as mailed from the EPO on Aug. 12, 2003, for International Application No. PCT/US03/03187, 6 pages.
Sun Microsystems Inc.
Tsai Henry W. H.
Zagorin O'Brien Graham LLP
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