Memory arbiter with grace and ceiling periods and...

Details Memory arbiter with grace and ceiling periods and... Memory arbiter with grace and ceiling periods and...

2006-04-25

2006-04-25

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S100000, C711S154000

Reexamination Certificate

active

07035984

ABSTRACT:
Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.

REFERENCES:
patent: 4365295 (1982-12-01), Katzman et al.
patent: 5699521 (1997-12-01), Iizuka et al.
patent: 5701494 (1997-12-01), Satoh
patent: 6006303 (1999-12-01), Barnaby et al.
patent: 6038631 (2000-03-01), Suzuki et al.
patent: 6058461 (2000-05-01), Lewchuk et al.
patent: 6681293 (2004-01-01), Solomon et al.

Affiliated with

Also associated with

Rating

Memory arbiter with grace and ceiling periods and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory arbiter with grace and ceiling periods and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory arbiter with grace and ceiling periods and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3553198