Delay locked loop

Details Delay locked loop Delay locked loop

2006-03-21

2006-03-21

Patel, Jay K. (Department: 2637)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S374000, C375S375000

Reexamination Certificate

active

07016452

ABSTRACT:
A delay locked loop includes a delay unit with a controllable delay time. Switching elements are provided in order to tap off output signals from the delay elements of the delay unit. Two nodes connected to the switching elements are connected to a multiplexer configuration in order to activate in each case two of the switching elements that are connected to delay elements connected directly in succession. A phase interpolator generates an intermediate phase from the signals provided.

REFERENCES:
patent: 6232812 (2001-05-01), Lee
patent: 6292116 (2001-09-01), Wang et al.
patent: 6639956 (2003-10-01), Song
patent: 6727738 (2004-04-01), Tsukikawa
patent: 2002/0027964 (2002-03-01), Yoo et al.
patent: 195 33 414 (1997-01-01), None
patent: 197 01 937 (1997-07-01), None
patent: WO 98/37656 (1998-08-01), None

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