Programmable CPU/interface buffer structure using dual port RAM

Details Programmable CPU/interface buffer structure using dual port RAM Programmable CPU/interface buffer structure using dual port RAM

2006-05-30

2006-05-30

Perveen, Rehana (Department: 2112)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S022000, C710S052000, C710S056000, C710S308000

Reexamination Certificate

active

07054986

ABSTRACT:
Disclosed is a programmable buffer circuit (16) for interfacing a CPU (12) to a plurality of channel interfaces (14). The buffer circuit includes a dual port memory (18) having a first port coupled to a CPU data bus and a second port coupled to a channel data bus that serves the plurality of channel interfaces. The buffer circuit further includes an arbitrator (24) for arbitrating access to the dual port memory by individual ones of the channel interfaces over the channel data bus; an address generator (26) for generating dual port memory addresses for reading and writing data using the CPU data bus and the channel data bus; and a control unit (20) and allocator (22) that are programmable by the CPU for specifying individual ones of buffer locations and sizes within the dual port memory for individual ones of the channel interfaces, and for enabling and disabling individual ones of the buffers.

REFERENCES:
patent: 4839791 (1989-06-01), Ito
patent: 5072420 (1991-12-01), Conley et al.
patent: 5386532 (1995-01-01), Sodos
patent: 5388237 (1995-02-01), Sodos
patent: 5784649 (1998-07-01), Begur et al.
patent: 5797043 (1998-08-01), Lewis et al.
patent: 5963499 (1999-10-01), Leong et al.
patent: 6044225 (2000-03-01), Spencer et al.
patent: 6058149 (2000-05-01), Sato
patent: 6081852 (2000-06-01), Baker
patent: 6122680 (2000-09-01), Holm et al.
patent: 6226338 (2001-05-01), Earnest
patent: 6242946 (2001-06-01), Veenstra
patent: 6263390 (2001-07-01), Alasti et al.
patent: 6330626 (2001-12-01), Dennin et al.
patent: 6400635 (2002-06-01), Ngai et al.
patent: 6470409 (2002-10-01), Ridgeway
patent: 0550163 (1992-07-01), None

Affiliated with

Also associated with

Rating

Programmable CPU/interface buffer structure using dual port RAM does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable CPU/interface buffer structure using dual port RAM, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable CPU/interface buffer structure using dual port RAM will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3551744