Method and system for memory access arbitration for...

Details Method and system for memory access arbitration for... Method and system for memory access arbitration for...

2006-07-18

2006-07-18

Peugh, Brian R. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S167000, C711S147000, C710S040000

Reexamination Certificate

active

07080194

ABSTRACT:
A method and system for arbitrating among memory access commands from clients seeking access to a DRAM or other memory, and an arbiter for use in implementing such method or system. When arbitrating among competing commands that include at least one command of the same read/write type as the current command, the arbiter selects a command of the same read/write type as the current command. In a wait mode, when arbitrating among a set of the commands that includes no command of the same read/write type as the current command, the arbiter prevents each command in the set from reaching the memory. Preferably, after operating in the wait mode for a limited time, the arbiter enters another arbitration mode in which it can select a command of the opposite read/write type as the current command. Preferably, the arbiter is implemented to be operable in any of multiple operating modes. For example, it can have separately programmable wait times for “read to write” and “write to read” situations. Preferably, the arbiter monitors for occurrence of potential page fault conditions.

REFERENCES:
patent: 6112265 (2000-08-01), Harriman et al.
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patent: 2003/0177320 (2003-09-01), Sah et al.
Miyano, et al., “A 1.6 Gbyte/s Data Transfer Rate 8 Mb Embedded DRAM”, © 1995 IEEE, p. 1281-1285.

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