Method and apparatus for monitoring component latency drifts

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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C714S815000

Reexamination Certificate

active

07076697

ABSTRACT:
A method and apparatus for monitoring the response times of computer system components in order to improve computer system reliability and performance are provided. The method and apparatus are particularly applicable to computer systems with memory circuits, such as SLDRAMs, that have programmable response times. A response time monitoring circuit in the form of a phase detector includes a plurality of flip-flops with the data inputs commonly connected to receive a response ready signal from a component, such as a memory circuit, in response to a command to perform a task. Each clock input of the flip-flop is connected to a clock signal at a different phase of a response period. The outputs of the flip-flops determine the phase at which the response ready signal was generated by the component.

REFERENCES:
patent: 4378509 (1983-03-01), Hatchett et al.
patent: 4564943 (1986-01-01), Collins et al.
patent: 4577318 (1986-03-01), Whitacre et al.
patent: 4646297 (1987-02-01), Palmquist et al.
patent: 4837521 (1989-06-01), Herlein et al.
patent: 5278974 (1994-01-01), Lemmon et al.
patent: 5444859 (1995-08-01), Baker et al.
patent: 5488309 (1996-01-01), Farwell
patent: 5533037 (1996-07-01), Shah et al.
patent: 5579326 (1996-11-01), McClure
patent: 5761274 (1998-06-01), Uehara et al.
patent: 5809034 (1998-09-01), Rezvani et al.
patent: 5831461 (1998-11-01), Dawe
patent: 5872976 (1999-02-01), Yee et al.
patent: 5978284 (1999-11-01), Pawlowski
patent: 6002282 (1999-12-01), Alfke
patent: 6031770 (2000-02-01), Pawlowski
patent: 6088830 (2000-07-01), Blomgren et al.
patent: 6092030 (2000-07-01), Lepejian et al.
patent: 6108795 (2000-08-01), Jeddeloh
patent: 6151682 (2000-11-01), van der Wal et al.
patent: 6184753 (2001-02-01), Ishimi et al.
patent: 6192092 (2001-02-01), Dizon et al.
patent: 6298465 (2001-10-01), Klotchkov
patent: 6341326 (2002-01-01), Zhao et al.
patent: 6370200 (2002-04-01), Takahashi
patent: 6374371 (2002-04-01), Lee
patent: 6421801 (2002-07-01), Maddux et al.
patent: 6449727 (2002-09-01), Toda
patent: 6560716 (2003-05-01), Gasparik et al.
patent: 6577175 (2003-06-01), Kim
patent: 6637018 (2003-10-01), Demler
patent: 6665823 (2003-12-01), Lee
patent: 6820234 (2004-11-01), Deas et al.
patent: 6842864 (2005-01-01), Hampel et al.
patent: 2002/0046288 (2002-04-01), Mantegna et al.
patent: 2002/0097822 (2002-07-01), Mantegna et al.
400 Mb/s/pin SLDRAM, CONS400.PG5-Rev. Sep. 22, 1997.
Draft Standard for a High-Speed Memory Interface (SyncLink), Draft 0.99 IEEE P1596.7-199X, Sponsor Microprocessor and Microcomputer Standards Subcommittee of the IEEE Computer Society, Copyright 1996 IEEE.

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