Memory array with low power bit line precharge

Details Memory array with low power bit line precharge Memory array with low power bit line precharge

2006-07-25

2006-07-25

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including signal clamping

C365S185200, C365S185210, C365S185250

Reexamination Certificate

active

07082061

ABSTRACT:
An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Clamp transistors are coupled to respective bit lines in the array, and adapted to prevent voltage on the respective bit lines from exceeding a target level. A comparator has an input coupled to the reference bit line and an output coupled to the clamp transistors on the plurality of bit lines. The comparator generates a bias voltage which turns on the clamp transistors at a first bias level when the reference bit line has a voltage below the target level, and a second bias level, which is lower than the first bias level, when the reference bit line has a voltage near the target level.

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