Self-aligned trench DMOS transistor structure and its...

Details Self-aligned trench DMOS transistor structure and its... Self-aligned trench DMOS transistor structure and its...

2006-09-19

2006-09-19

Owens, Douglas W. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S330000

Reexamination Certificate

active

07109552

ABSTRACT:
A self-aligned trench DMOS transistor structure of the present invention comprises a self-aligned source structure and a self-aligned trench gate structure, in which the self-aligned source structure comprises a p-base diffusion region, a self-aligned n+source diffusion ring, a self-aligned p+contact diffusion region, and a self-aligned source contact window; the self-aligned trench gate structure comprises a self-aligned silicided conductive gate structure, a self-aligned polycided conductive gate structure or a self-aligned polycided trenched conductive gate structure. The self-aligned trench DMOS transistor structure as described is fabricated by using only one masking photoresist step and can be easily scaled down to obtain a high-density trench DMOS power transistor with ultra low on-resistance, low gate-interconnection parasitic resistance, and high device ruggedness.

REFERENCES:
patent: 6916712 (2005-07-01), Kocon et al.
patent: 2002/0158277 (2002-10-01), Harada et al.

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