SOI device with reduced junction capacitance

Details SOI device with reduced junction capacitance SOI device with reduced junction capacitance

2006-03-07

2006-03-07

Blum, David S. (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

07009251

ABSTRACT:
An SOI FET comprising a silicon substrate having silicon layer on top of a buried oxide layer having doped regions and an undoped region is disclosed. The doped region has a dielectric constant different from the dielectric constant of the doped regions. A body also in the silicon layer separates the source/drains in the silicon layer. The source/drains are aligned over the doped regions and the body is aligned over the undoped region. A gate dielectric is on top of the body and a gate conductor is on top of the gate dielectric.

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Badith El-Kareh et al “Silicon on Insulator—An Emerging High-Leverage Technology” IEEE1994 pages 224-233.

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