Apparatus for random access memory array self-test

Details Apparatus for random access memory array self-test Apparatus for random access memory array self-test

2006-05-30

2006-05-30

Decady, Albert (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

07055075

ABSTRACT:
An apparatus for the on-chip testing of random access memory arrays. In representative embodiments, embedded circuitry provides the ability to test random access memory arrays on-chip without requiring substantial area on the chip. The circuits are inherently located closer to the tested area which reduces propagation delay errors. These advantages have been obtained by locating the circuitry necessary to perform such test in the addressing and input/output blocks of the RAM.

REFERENCES:
patent: 5301156 (1994-04-01), Talley
patent: 6408401 (2002-06-01), Bhavsar et al.
patent: 6609222 (2003-08-01), Gupta et al.
U.S. Appl. No. 10/679,928, filed Oct. 6, 2003, Koss et al.
U.S. Appl. No. 10/021,614, filed Dec. 5, 2001, Koss et al.

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