Imprecise cache line protection mechanism during a memory...

Details Imprecise cache line protection mechanism during a memory... Imprecise cache line protection mechanism during a memory...

2006-01-10

2006-01-10

Verbrugge, Kevin (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S148000

Reexamination Certificate

active

06986013

ABSTRACT:
A method for avoiding livelock within a multiprocessor data processing system when there are multiple, concurrent clone operations to similar memory data locations within a data processing system. A set of tokens are defined within the memory cloner for use prior to conducting a clone operation on the fabric. The tokens include a source token and a destination token. The tokens are issued on the fabric by a memory cloner prior to initiating the data clone operation. The tokens discover the availability of a source address and a destination address required to complete the clone operation. Once the response to the destination address token indicates that the destination address is not currently being utilized by another memory cloner to conduct another data clone operation, the memory cloner may issue the commands to initiate the memory clone operation.

REFERENCES:
patent: 6128714 (2000-10-01), Onodera
patent: 6393540 (2002-05-01), Blumenau et al.
patent: 6529968 (2003-03-01), Anderson
patent: 6665783 (2003-12-01), Zahir
patent: 6721851 (2004-04-01), Ohr
patent: 6813522 (2004-11-01), Schwarm et al.
patent: 6883076 (2005-04-01), Ohr
patent: 6895483 (2005-05-01), Eguchi et al.
patent: 2003/0153306 (2003-08-01), Study et al.

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