Memory device having different burst order addressing for...

Details Memory device having different burst order addressing for... Memory device having different burst order addressing for...

2006-07-25

2006-07-25

Verbrugge, Kevin (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S167000, C711S217000, C710S035000

Reexamination Certificate

active

07082491

ABSTRACT:
An apparatus enables the reordering of a block of n-bit words output from a plurality of memory cells according to information in certain address bits before outputting at least one n-bit word from a memory device while ignoring those certain address bits before inputting at least one n-bit word into the plurality of memory cells. The apparatus may additionally comprise examining at least two of the least significant bits of a column address and wherein the reordering is responsive to the examining. Thus, for reads a specific 8 bit burst is identified by the most significant column address bits while the least significant bits CA0–CA2identify the most critical word and the read wrap sequence after the critical word. For writes, the burst is identified by the most significant column addresses with CA0–CA2being “don't care” bits assumed to be 000.

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patent: 6931483 (2005-08-01), Janzen

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