Single poly-si process for DRAM by deep N-well (NW) plate

Details Single poly-si process for DRAM by deep N-well (NW) plate Single poly-si process for DRAM by deep N-well (NW) plate

2006-04-18

2006-04-18

Kang, Donghee (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S300000, C257S301000, C257S304000, C257S305000, C438S238000, C438S239000, C438S242000

Reexamination Certificate

active

07030440

ABSTRACT:
A method for forming, within a double well formation, an array of DRAM memory cells isolated from each other by shallow trench isolation (STI), each cell comprising a MOSFET access transistor and a storage trench capacitor. A top plate of said capacitor is the trench wall within a deep N-well portion of the double well and the bottom plate is formed of a doped polysilicon layer within the trench, which layer is partially separated from the trench sidewalls by a dielectric layer whose upper portion is removed to allow the formation of a autodiffused doped channel between said polysilicon plate and the source region of the access transistor. The method uses a single dielectric layer deposition to serve as both a gate dielectric for the MOSFET and a capacitor dielectric and requires only a single deposition of polysilicon to serve as both the transistor gate electrode and a capacitor plate.

REFERENCES:
patent: 4794434 (1988-12-01), Pelley, III
patent: 5998821 (1999-12-01), Hieda et al.
patent: 6300683 (2001-10-01), Nagasaka et al.

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