Refresh control and internal voltage generation in...

Details Refresh control and internal voltage generation in... Refresh control and internal voltage generation in...

2005-08-16

2005-08-16

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S236000, C365S189090

Reexamination Certificate

active

06930946

ABSTRACT:
The present invention provides a technique of mitigating the long cycle limitation in a semiconductor memory device that requires refresh operation. A semiconductor memory device comprises a refresh controller that executes refresh operation. The refresh controller comprises: a refresh timing signal generator, a refresh request signal generator, and a refresh execution signal generator. The refresh request signal generator comprises: a first counter that counts the number of times the refresh timing signal has been generated; and a second counter that counts the number of times the refresh execution signal has been generated. The refresh request signal generator generates the refresh request signal if a difference of the two number of times of signal generation is one or more. The refresh execution signal generator is capable of generating two or more of the refresh execution signals within one cycle of the refresh timing signal if the difference is two or more.

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