Method of routing a redistribution layer trace in an...

Details Method of routing a redistribution layer trace in an... Method of routing a redistribution layer trace in an...

2005-08-02

2005-08-02

Whitmore, Stacy A. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06925626

ABSTRACT:
A method of routing a metal layer trace in an integrated circuit die includes steps of: (a) receiving as input a netlist of an integrated circuit die; (b) selecting a redistribution layer trace from the netlist for routing the redistribution layer trace between an I/O pad of the integrated circuit die and a termination point; (c) comparing a trace width of the redistribution layer trace with a maximum trace width limit; and (d) if the trace width of the redistribution layer trace exceeds the maximum trace width limit, then routing the redistribution layer trace as a plurality of separate parallel traces each having a trace width that is less than the selected maximum trace width limit.

REFERENCES:
patent: 6230306 (2001-05-01), Raspopovic et al.
patent: 6810512 (2004-10-01), Roohparvar
patent: 6826741 (2004-11-01), Johnson et al.

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