Tri-gate devices and methods of fabrication

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S157000, C438S283000

Reexamination Certificate

active

06858478

ABSTRACT:
The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

REFERENCES:
patent: 5563077 (1996-10-01), Ha
patent: 5578513 (1996-11-01), Maegawa
patent: 5658806 (1997-08-01), Lin et al.
patent: 5716879 (1998-02-01), Choi et al.
patent: 6376317 (2002-04-01), Forbes et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 6475869 (2002-11-01), Yu
patent: 6483156 (2002-11-01), Adkisson et al.
patent: 6611029 (2003-08-01), Ahmed et al.
patent: 6680240 (2004-01-01), Maszara
patent: 6716684 (2004-04-01), Krivokapic et al.
patent: 20020081794 (2002-06-01), Ito
patent: 20020167007 (2002-11-01), Yamazaki et al.
patent: 0623963 (1994-11-01), None
patent: WO 0243151 (2002-05-01), None
Jong-Tae Park, Pi-Gate SOI MOSFET, IEEE Electron Device Letters, vol. 22, No. 8, Aug. 2001.
Digh Hisamoto et al. Fin FET—A Self Aligned Double-Gate MOSFET Scalable to 20 nm, IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000.
International Search Report PCT/US 03/26242.
International Search Report PCT/US03/39727.
International Search Report PCT/US 03/40320.
V. Subramanian et al., “A Bulk-Si-Compatible Ultrathin-body SOI Technology for Sub-100m MOSFETS” Proceeding of the 57th Annual Device Research Conference, pp. 28-29 (1999).
Hisamoto et al., “A Folded-channel MOFSET for Deepsub-tenth Micron Era”, 1998 IEEE International Electron Device Meeting Technical Digest, pp. 1032-1034 (1998).
Huang et al., “Sub 50-nm FinFET: PMOS”, 1999 IEEE International Electron Device Meeting Technical Digest, pp. 67-70 (1999).
Auth et al., “Vertical, Fully-Depleted, Surroundings Gate MOSFETS On sub-0.1um Thick Silicon Pillars”, 1996 54th Annual Device Reserch Conference Digest, pp. 108-109 (1996).
Hisamoto et al., “A Fully Depleted Lean-Channel Transistor (DELTA)-A Novel Vertical Ultrathin SOI MOSFET”, IEEE Electron Device Letters, V. 11(1), pp. 36-38 (1990).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Tri-gate devices and methods of fabrication does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Tri-gate devices and methods of fabrication, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Tri-gate devices and methods of fabrication will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3514052

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.