Circuit and method for improving noise tolerance in...

Details Circuit and method for improving noise tolerance in... Circuit and method for improving noise tolerance in...

2005-02-01

2005-02-01

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S095000, C326S098000

Reexamination Certificate

active

06850093

ABSTRACT:
An embodiment of the invention provides a circuit and method for improving noise tolerance in multi-threaded memory circuits. A PFET is added to the receiving input of each memory cell. The gate of the PFET is connected to the output of the memory cell and the source of the PFET is connected to the control signal of the memory cell. In the case where the dataline is charged near ground and a memory cell, with a high value, is read, and the control signal is high, noise tolerance is improved by the addition of the PFET to the memory cell. The invention does not introduce additional drive fights during writes, when the control signal is low.

REFERENCES:
patent: 6420903 (2002-07-01), Singh et al.
patent: 6629236 (2003-09-01), Aipperspach et al.

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