Bus network interface

Electronic digital logic circuitry – Signal sensitivity or transmission integrity

Reexamination Certificate

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Details

C326S014000, C327S020000

Reexamination Certificate

active

06933745

ABSTRACT:
A system and method for transmitting data includes one or more transmitters connected to each of at least one bus data line via open-driver bus data line drivers, and one or more receivers. In a preferred embodiment, the devices are interconnected by a parallel interface using a bus architecture having the bus data and carrier-sense (CRS) lines each driven by open-collector or open-drain drivers in a wired-and configuration. Pullup resistors and a common clock signal are also provided. Each device is provided with an interfacing unit which connects the device to the bus, and detects collisions by comparing data transmitted by the device with data received from the bus. The invention is particularly applicable to implementation as a backplane connecting intercommunicating printed wiring boards having interfaces such as the IEEE 802.3 (Ethernet) Media Independent Interface (MII), the interfacing unit serving to emulate the Ethernet PHY.

REFERENCES:
patent: 6211694 (2001-04-01), Kamiya
patent: 6411122 (2002-06-01), Mughal et al.
patent: 6822480 (2004-11-01), McCalmont
Chapter 22 “Reconciliation Sublayer (RS) and Media Independent Interface (MII)” in the IEEE 802.3 standard “Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer specifications”, 2000, no month.

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