Semiconductor memory device and manufacturing method of the...

Details Semiconductor memory device and manufacturing method of the... Semiconductor memory device and manufacturing method of the...

2005-11-15

2005-11-15

Thompson, Craig (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

Reexamination Certificate

active

06965148

ABSTRACT:
In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.

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