Ferroelectric random access memory capacitor and method for...

Details Ferroelectric random access memory capacitor and method for... Ferroelectric random access memory capacitor and method for...

2005-11-08

2005-11-08

Vu, Hung (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000, C257S303000, C257S306000

Reexamination Certificate

active

06963097

ABSTRACT:
The method for manufacturing an FeRAM capacitor with a merged top electrode plate line (MTP) structure is employed to prevent a detrimental impact on the FeRAM and to secure a reliable FeRAM device. The method includes steps of: preparing an active matrix obtained by a predetermined process; forming a first conductive layer, a dielectric layer and a second conductive layer on the active matrix in sequence; forming a hard mask on the second conductive layer; patterning the second conductive layer, the dielectric layer and the first conductive layer by using the hard mask, thereby forming a vertical capacitor stack, a width of the capacitor stack being larger than that of the storage node contact; forming a second ILD embracing the capacitor stack; planarizing the second ILD till the top face of the hard mask is exposed; removing the hard mask to form an opening above the top electrode; and forming a plate line of which a width is larger than that of the capacitor stack.

REFERENCES:
patent: 6249014 (2001-06-01), Bailey
patent: 6326216 (2001-12-01), Kato et al.
KR Laid-Open No. 2003-23844.
0.18 μm SBT-Based Embedded FeRAM Operating at a Low Voltage of 1.1V (2003 Symposium on VLSI Technology Digest of Technical Papers).
Highly Manufacturable and Reliable 32 Mb FRAM Technology with Novel BC and Capacitor Cleaning Process (2003 Symposium on VLSI Technology Digest of Technical Papers).

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