Multiple port system and method for controlling the same

Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area

Reexamination Certificate

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Details

C711S001000, C711S002000, C370S392000

Reexamination Certificate

active

06970983

ABSTRACT:
A multiple port system includes a plurality of port devices, each port device including a control register set, and a control bus coupled to the plurality of port devices. The control bus provides a control signal to each port device, and the control signal includes port address information and register address information. The control register set includes a set of registers responsive to the control signal if the port address information indicates the corresponding port device, and a designated register responsive to the control signal if the port address information indicates one of the plurality of the port devices and the register address information indicates the designated register.

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patent: 5784003 (1998-07-01), Dahlgren
patent: 5802052 (1998-09-01), Venkataraman
patent: 6011799 (2000-01-01), Kerstein et al.
patent: 6205493 (2001-03-01), Dreyer et al.
patent: 6389480 (2002-05-01), Kotzur et al.
patent: 6697887 (2004-02-01), Acharya
“Etherent PHY-110 Core”, DB08-000181-00 Mar. 2002, pp. 1-17.

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