Integrated circuit

Details Integrated circuit Integrated circuit

2005-06-21

2005-06-21

Tran, Thien F (Department: 2811)

Static information storage and retrieval

Read/write circuit

Noise suppression

C365S214000, C365S230030, C365S230060

Reexamination Certificate

active

06909655

ABSTRACT:
A plurality of decoding circuits1ato1fare arranged near a plurality of circuit blocks2to7, which are arranged on the semiconductor chip10in a scattered manner, and the signal lines8prior to decoding, including the address lines and the data lines, are wired to each decoding circuit1ato1f. Through these wirings, the number of wirings routed over on the semiconductor chip10can be made in accordance with the number of bits of the signal lines8alone. So, compared with the past where the signal lines20, which were great in number after decoding, were routed over to each circuit block2to7, the wiring area as a whole can be greatly reduced. This can lead to miniaturization of chip size, reduction of crosstalk noise, and facilitation of layout.

REFERENCES:
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patent: 2000-347890 (2000-12-01), None
patent: 2001-077311 (2001-03-01), None
patent: 162395 (1991-07-01), None

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