Semiconductor device and method for manufacturing the same

Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Diffusing a dopant

Reexamination Certificate

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C438S527000, C438S530000, C438S529000, C438S531000, C257S061000, C257S405000

Reexamination Certificate

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06852610

ABSTRACT:
A semiconductor device includes a gate electrode formed on a semiconductor region via a gate insulative film and an extension high concentration diffusion layer of a first conductivity type formed in the semiconductor region beside the gate electrode. A dislocation loop defect layer is formed in a region of the semiconductor region beside the gate electrode and at a position shallower than an implantation projected range of the extension high concentration diffusion layer.

REFERENCES:
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patent: 6013546 (2000-01-01), Gardner et al.
patent: 6030863 (2000-02-01), Chang et al.
patent: 6078081 (2000-06-01), Lee
patent: 6087209 (2000-07-01), Yeap et al.
patent: 62-200723 (1987-09-01), None
patent: 03-174721 (1991-07-01), None
patent: 11-40801 (1999-02-01), None
patent: 2000-260728 (2000-09-01), None
M.C. Ozturk et al., “Very shallow p+-n junction formation by low-energy BF+2ion implantation into crystalline and germanium preamorphized silicon”, Appl. Phys. Lett. 52 (12), pp. 963-965, Mar. 1988.
Notice of Reasons of Rejection Dated Nov. 18, 2003.

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